Integrated circuit (IC) devices such as IC dies (hereinafter “dies”) and associated packaging configurations continue to shrink to smaller dimensions to accommodate mobile computing devices and other small form factor implementations. One emerging solution to couple IC devices may include the formation of through-silicon vias (TSVs) through a backside of a die to provide electrical routing through the die for another die. However, providing a landing structure for the TSVs on a frontside of the die may be challenging. For example, the TSVs may have a dimension that is much larger than a maximum dimension allowed by design rules for interconnect structures patterned in the interconnect layers of present dies. Such discrepancy in dimension of the TSVs with the dimensions of the design rules may preclude the formation of a single, contiguous landing structure that is commensurate in size with a TSV, particularly for lower interconnect layers closest to the transistors formed on the semiconductor substrate of the die where design rules are more stringent than for upper interconnect layers. Overlay and critical dimension variation in the formation of the interconnect structures may further exacerbate this challenge. It may be desirable to position the landing structure for a TSV formed from the backside of the semiconductor substrate in the interconnect layers closest to the semiconductor substrate of the die to avoid the challenges associated with penetrating multiple interconnect layers to connect to the landing structure.